This invention relates to a semiconductor integrated circuit, and more particularly to an input buffer capable fo preventing an erroneous operation occurring in an integrated circuit resulting from changes in a power supply potential or a ground potential produced at the time of outputting data.
In semiconductor integrated circuits, e.g., semiconductor memories, etc. there are instances where a large capacitor existing at the external, e.g., a load capacitor of about 100 pF is driven by an output buffer for outputting internal data to the external. The transistors of the output stage in the output buffer circuit have an extremely large current drive ability to charge or discharge in a short time the load capacitor.
FIG. 5 is a circuit diagram showing an example of an output buffer circuit 50 as mentioned above.
Internal data Di of the integrated circuit is applied to the input terminal 51 of the output buffer circuit 50. This output buffer circuit is in an enabling state, when the output enable signal OE1 and its ivnerted signal OE1 are a logic "1" and a logic "0", respectively. A P-channel MOS transistor 52 and an N-channel mOS transistor 53 which are controlled by the inverted signal OE1 are turned ON and OFF, respectively. The internal data Di is delivered to the gate of the P-channel MOS transistor 58 of the output stage through a substantial CMOS inverter comprised of a P-channel MOS transistor 54 and an N-channel MOS transistor 55 and a CMOS inverter comprised of a P-channel MOS transistor 56 and an N-channel MOS transistor 57 in order recited.
An N-channel MOS transistor 59 and a P-channel MOS transistor 60 which are controlled by the signal OE1 are turned ON and OFF, respectively. The internal data Di is delivered to the gate of an N-channel MOS transistor 65 of the output stage through a substantial CMOS inverter comprised of a P-channel MOS transistor 61 and an N-channel MOS transistor 62 and a CMOS inverter comprised of a P-channel MOS transistor 63 and an N-channel MOS transistor 64 in the order recited. The source of the transistor 58 of the output stage and the source of the transistor 65 of the output stage are connected to a positive power supply potential Vcc and a ground potential Vss, respectively, and the drains of the both transistors are commonly connected to the output terminal 66. A load capacitor 67 is connected to the output terminal 66.
In such an output buffer circuit, either of the transistors 58 and 65 of the respective output stages is turned ON in dependency upon the logic level of the internal data Di. When the transistor 58 is turned ON, the ouput terminal 66 is charged toward the power supply potential Vcc through the transistor 58 in an ON state, while when the transistor 65 is turned ON, the output terminal 66 is discharged toward the ground potential Vss. To rapidly charge and discharge the output terminal 66 connected an external large load capacitor 67, the current drive capability of each of the transistors 58 and 65 is large.
The power supply potential Vcc and the ground potential Vss are respectively delivered to this integrated circuit through the wiring L1 and L2 applied fro mpower source unit 70. The wiring L1 and L2 contain parasitic inductances 71 ad 72, respectively. Because of the presence of those inductances, the power supply potential Vcc and the ground potential Vss in this integrated circuit is varied, when the current Is or It (shown in FIG. 5) flows through the transistor 58 or 65 respectively for charging or discharging of the output terminal 66. Namely, when the value of each inductance 71 and 72 existing in the wiring and a ratio of changes in time of a current flowing in these wiring are designated by L and di/dt, respectively, a potential change .DELTA.v expressed as the following equation occurs: EQU .DELTA.v=L.multidot.di/dt (1)
FIG. 6 is a waveform diagram showing the voltage and current waveforms of respective componnts in the output buffer circuit 50. In this waveform diagram, Va represnts a gate potential of the P-channel MOS transistor 58 of the output stage, Vb a gate potential of the N-channel MOS transistor 65 of the output stage, Is a drain current (charge current) of the P-channel MOS transistor 58, and It a drain current (discharge current) of the N-channel MOS transistor 65.
As shown in FIG. 6, after the logic level of the internal data Di has changed, the gate potential Va of the P-channel MOS transistor 58 and the gate potential Vb of the N-channel MOS transistor 58 and the output stage change. Thus, these transistors 58 and 65 carry out switching operations, respectively. As a result, a drain current Is of the transistor 58 or a drain current It of the transistor 65 flows. Thus, a change in the Vcc potential or the Vss potential would occur by the flowing of this large current Is or It.
As stated above, as the result of the fact that a large current flows when data is outputted from the output buffer circuit, a potential change (hereinafter refered to as a power supply noise) in the power supply voltage Vcc and the ground potential Vss occurs inside the integrated circuit. This potential change may cause an erroneous operation in the integrated circuit. Where it is required to charge or discharge the external load capacitor in a shorter time for improvement of the high speed characteristic, such an erroneous operation caused by the charge/discharge current for the load capacitor is increasingly apt to take place because a larger current is required to flow.